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1 application note 1837 author: michael steffes ultra high performance broadband 12 to 16-bit data acquisition platform isla214p50-55210ev1z high speed adc/amp evaluation board 1. isla214p50 high speed, high performance adc (14-bit, 500msps) 2. isl55210 high performance, low power, fully differential amplifier (fda) 3. compatible with existing intersil high speed adc evaluation platforms 4. optional response measuremen t port from adc inputs to board edge 5. pin compatible family of 12-to-16 bit adc?s can be used on this board performance range 1. clock rate range: 80msps to 500msps 2. 283mv p-p input (-7.0dbm) for -2dbfs at adc inputs (1.6v p-p at adc) 3. 0.8db flat response from 100khz to 100mhz 4. typical snrfs (30mhz input, 500msps): 71.8dbfs (vs 72.6dbfs for adc only) 5. typical sfdr (30mhz input, 500msps): 89dbc (vs 84dbc for adc only) system requirements 1. isla214p50-55210ev1 z evaluation board 2. kmb-001levalz intersil motherboard (+5v supply provided with motherboard) 3. intersil konverter software http://www.intersil.com/content/intersil/en/products/dat a-converters/high-speed-a-d-converters/hs-adc-evaluation- platform.html 4. low jitter clock source 5. bandpass filters 6. pc running windows xp operating system with konverter software installed board numbering note the original board marking was isla214p50/55210ev1z. for ordering purposes, that has be en changed wherever possible to isla214p50-isl55210ev1z. any reference to isl214p50/55210ev1z would be the same end item as the final ordering number version with the dash instead slash. evaluation platform overview this isla214p50-55210ev1z is an evaluation platform featuring intersil?s ultra-high dynamic range fully differential amplifier (fda), the isl55210 , and the high speed, high performance, 14-bit, 500msps adc, the isla214p50. this pcb daughterboard mates to inte rsil?s existing high speed adc evaluation platform allowi ng for easy performance measurement and analysis (see intersil application notes an1433 , and an1434 for more information). the adc evaluation platform consists of custom designed hardware and software supporting a wide range of adc daughterboards on the kmb-001 motherboard. the function of the hardware is to provide power to the adc daughterboard, manage the communication to the adc internal settings, accept clock and signal inputs, and buffer the digital outputs for communication to a host pc. the konverter software is required to configure the adc for initial operation, to modify the device functionality or parameters, and to process and display the captured digital data. konverter software version 1.22c (or later) supports the isla214p50 family and the isla214p50-55210ev1z pcb. contact the factory for assistance in using the konverter software to modify this board to a different adc in the pin compatible family. table 1. pin compatible high performance adc family part number resolution (bits) maximum sample rate (msps) power consumption (mw) isla216p25 16 250 785 isla216p20 16 200 720 isla216p13 16 130 615 isla214p50 14 500 835/900 (note) isla214p25 14 250 450 isla214p20 14 200 410 ISLA214P13 14 130 360 isla214p12 14 125 310 isla212p50 12 500 823/892 (note) isla212p25 12 250 440 isla212p20 12 200 405 isla212p13 12 130 355 note: i2e disabled/enabled. caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas llc 2013. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners. may 3, 2013 an1837.0
application note 1837 2 an1837.0 may 3, 2013 operating precautions:!! it is strongly recommended to insert the +5v plug at the motherboard prior to plugging in the ac adapter to reduce the possibility of power surges which can damage the pcb. probing on the pcb should be done with care using proper esd techniques while handling. hardware description there are two components in the hardware portion of the evaluation platform. the daughtercard and the motherboard (figure 1). the fda and adc are on the daughtercard, which accepts power from the motherbo ard and contains the analog input circuitry, clock interface, and supply decoupling. the daughtercard interfaces to the motherboard through a mezzanine connector. the motherboard contains a usb interface, an fpga and sram. the motherboard serves as the interface between the host pc and the adc daughtercard. most of the adc functionality is controlled through the motherboard by the konverter software. the fpga accepts output data from the adc and buffers it to the srams before passing it to the pc at the lower data rate required for post-processing. the maximum buffer depth is approximately one million words. the designer must supply a low jitter rf generator for the clock input to achieve the snr reported here. some possible options are shown in ?appendix a: low phase noise rf generators? on page 15. an alternate to a signal generator for fixed 500msps clock rates would be the 3.3v supply, sma barrel, rfpro33-500 from crystek. a slight degradation in snr might be expected using this device vs the best low phase noise rf signal generators and a bandpass filter on the clock. using a bandpass filter on the clock will reduce clock jitter and improve snr while using a bandpass on the signal so urce is normally required to eliminate harmonics while testing the board performance. most rf generators that might be used as a test analog input source have very poor harmonic distortion and require a bandpass postfilter to see the full performance of the adc?s fft. software description the software component is the konverter analyzer, a graphical user interface (gui) created with matlab?. a matlab component runtime engine is supplied, which executes a compiled version of the m-files. therefore, a separate version of matlab is not required to run the konverter analyzer. the gui controls the adc configur ation through its spi port, reads data from the motherboard and pe rforms the post-processing and display of digitized data. data can be viewed in either the time or frequency domain, and can be save d for later processing. critical performance parameters such as snr, sfdr, enob, etc. are calculated and displayed on th e screen when fft output is selected and a dominant single frequency is being applied. initial start-up referring to figure 3, conn ect the daughtercard to the motherboard by aligning the two matching mezzanine connectors. four screws on the motherboard align with the mounting holes on the daughtercard. next, connect the clock source ( 12dbm level into 50 ? ) which will be required for communication to the konverter software. then connect a test source or signal of interest coming from your signal chan nel at a maximum input level <350mv p-p (or <-5.1dbm for single tone). with the rf signal generators delivering a clock and input signal to the daughtercard, and the +5v supply jack plugged into the motherboard, plug the ac power plug into a wall socket. the daughtercard is powered from linear regulators on the motherboard through the mezzanine connector. the usb cable should now be connected from the motherboard to the pc. be sure to use the same usb port that was originally used when the konverte r software was installed on the pc to insure it is recognized. now launch the konverter software on the pc where it should recogniz e the motherboard and proceed to taking an fft. motherboard the only connections to the motherboard are the +5v supply power and the usb cable to the pc with the konverter software loaded. no additional configuration of the motherboard is required. it is strongly recommended to insert the +5v plug at the motherboard with the daughterboard attached prior to plugging in the ac adapter to reduce the possibility of power surges which can damage the pcb. probing on the pcb?s should be done with care and proper esd procedures used when handling the boards. figure 1. typical characterization setup using the intersil kmb-001 motherboard and konverter software low-jitter rf generator clock inputs analog input low-jitter rf generator 10mhz reference mezzanine connector usb to host pc analog input clock (200-500mhz) ref in ref out motherboard kmb001 usb +5v fpga sram sram adc daughter card optional attenuator amp optional measurement port test bandpass filter
application note 1837 3 an1837.0 may 3, 2013 software start-up the fpga clock is derived from the adc output clock, and the fpga clock must be active for the software to operate correctly. therefore, it is critical to have a convert clock present and the board powered up before the konverter software is launched. it is not necessary to have an analog input signal present. the compressed matlab files are unpacked the first time the gui is invoked after installation. this will slow the start-up the first time the evaluation system is used but it will run more quickly in subsequent startups. complete information can be found in the kmb-001 installer manual at: http://www.intersil.com/converters/adc_eval_platform/ the main konverter analyzer window is shown in figure 16. the application opens in fft mode by default, but other modes can be selected using the radio buttons in the lower left corner. in each mode, relevant parameters are displayed in the data box the left side of the window. the following data is displayed in all operating modes ? 1. fsamp: sample clock freque ncy, automatically detected. 2. ffund: input frequency, automatically detected if input is a single tone or dominant tone waveform 3. fund: amplitude of the dominant tone in dbfs 4. samples: record length, defaults but can be updated data acquisition normally, the first step to an fft data display is to open the ?setup? key in the upper left and pick a windowing function to limit spectral leakage. all the plots and data here used the blackman harris 4 term windowing. it is also possible to change the record length for the fft in this screen. normally, the continuous calibration and backgrou nd keys are selected and, if desired, an averaging of the fft outputs may be selected in the lower left of the konverter screen set up for fft display (default at start-up). then, press ?run? in the lower left and the fft will be updating. the number of averaged sweeps defaults to 10, but can also be changed in the ?setup? conditions dialog window. menu items and the toolbar buttons may not function properly if data is being captured continuously . press ?stop? in the lower left before selecting a menu item or using a toolbar button. an1433 should be consulted for more information on the options provided in the konverter windows. an1434 offers help for first time installation if needed. hardware and analog signal path description figure 2 shows a close-up of the isla214p50-55210ev1z daughtercard. the sma at the top left is the an alog input connection, the next one down is an optional sense po rt for an attenuated version of the differential signal being presented to the adc input pins, while the lower sma is the clock input pin. several optional inputs are not populated, like the amplifier disable control line at the lower left of the card and some alternate clock input paths on the bottom. the v test path sma is not populated on the board as delivered but may be easily added. figure 2. isla214p50-55210ev1z daughterboard
application note 1837 4 an1837.0 may 3, 2013 the analog input signal comes in through 2-minicircuits transformers then into the isl55210 then into an interstage passive rlc filter to the adc. the blue potentiometer in the middle of the board is a common mode voltage adjustment for the average dc voltage applied to the adc inputs for this ac coupled signal path. this board plugs into the kmb-001 motherboard to appear as in figure 3. here, the input signal is connected and the 500mhz clock is being applied through a tte 500mhz bandpass filter. the power is being applied to the motherboard as shown by the active green light just under the +5v power connector in the upper right. again, the +5v board connector is plugged in first, then the ac plug inserted to the power allowing the power brick to filter the +5v power up transient. similarly on power down, unplug the +5v power at the ac plug side. while the full signal path schematic is shown in figure 46, it is best to break it into pieces for discussion of design, performance, and options. in general, the bo ard offers numerous optional connections that are indicated in green on the schematic and/or by dnp for the standard board build. the basic signal path is intended to: 1. terminate a single ended input with an ac-coupled, broadband, 50 ? impedance. this is of course expecting the source to also be a broadband 50 ? source and that impedance does get reflected through the input transformers to be part of the signal chain flatness characteristic. 2. convert the single ended input to the required differential signal at the adc inputs centered within the converter?s desired common mode voltage range. 3. provide amplification from a nominal -7dbm (283mv p-p ) single tone input to a -2dbfs (2db below the 2v p-p full scale of the adc) or 1.58v p-p at the adc input pins with extremely low noise and distortion. this 5.6v/v gain (15db) gain is a combination of the input transformer step up, isl55210 gain, and various insertion losses in the transformers and interstage filter from the isl55210 to the adc. 4. as part of the interstage filter design, this board includes a v cm control loop that senses the average dc voltage at the two adc inputs and servo?s a control voltage into the filter design to match a reference volt age applied to the servo loop op amp. the board is delivered set to 0.96v as that has shown improved sfdr for the filter source impedance and the isla214p50 adc. changing adc selections and/or filter designs in this board might benefit from a different nominal v cm control target for best sfdr and the v cm adjust pot allows and easy means to test that. amplifier power supply decoupling issues the portion of the signal path schematic of figure 4 shows one example of good power supply decoupling for this single 3.3v supply amplifier. where possible, a large valued capacitor isolated towards this 4ghz amplifier with a high frequency ferrite and then another 1f element provides a pi filter on the board. right at the 2 device supply pins, x2y capacitors are used to get the best high frequency deco upling. these 0.1f elements actually are two capacitors connected in parallel to give 0.2f decoupling with much lower es r and higher self resonant frequency than typical ceramic smd capacitors. standard smd 0.1f ceramic capacitors can be used instead but may increase the even order harmonics at higher frequencies as they go self resonant. those are provisioned on the board as optional elements but not populated as shown in figure 4 by the green capacitors c1003 and c1008. figure 3. isla214p50-55210ev1z daug hterboard on kmb-001 motherboard
application note 1837 5 an1837.0 may 3, 2013 input side circuit design and options as delivered, the interface uses an input transformer that is very flat to low frequencies followed by a common mode choke transformer that is a dc short for biasing with <0.3db insertion loss to >1ghz for the differential signal. either may be removed and replaced by shorts or resistor elements using the bypass resistors. the input signal is coupled through a 1 f blocking cap (to protect against accidental dc shorts) to an input step up transformer and then directly into a common mode choke transformer. the 1:2 turns (1:4 ? ) ratio step up transformer offers many advantages combined with an fda as shown here. the second transformer provides a differential signal short but a common mode open circuit. differentially, the two 100 ? gain resistors appear directly at the output of the input step up transformer. briefly, the 2-100 ? series resistors feed into a differential virtual ground at the fda summing junctions (r1009&r1010 in figure 4) and form a 200 ? differential termination impedance for the adt4-6t. that is input referred as a broadband 50 ? termination impedance out of the 1 f blocking cap. scaling these resistors up, while still maintaining a 200 ? secondary termination, can be done using the rterm1 element. this is sometimes useful at lower gain targets to allow the feedback resistors (r1008 & r1011) to be scaled up when they might be adding significant loading to th e output stage of the isl55210. detailed specifications for 4ghz gain bandwidth product, 0.85nv/ hz input noise isl55210 may be found at: http://www.intersil.com/products/isl55210 the isl55210 provides duplicates of the differential outputs on the input side for tighter signal path layout. the feedback resistors are the 2 -500 ? elements where the connection back into the inverting summing junctions are the 0 ? elements. neglecting transformer insertion losses, the gain from the input port to the amplifier outputs should be 2 (in the first transformer) x 5 (in the fda) = 10 (or 20db). the adt4-6t was selected primarily for its excellent flatness and distortion down to 100khz. its measured response showed a -1db flatness span from 40khz to 178mhz when driven from 50 ? to 200 ? load with a -0.18db midband insertion loss. this is a suitable frequency span for the intended 100khz to 100mhz digitizer bandwidth in this board. it does show a bit of rolloff at 100mhz which is partially equalized by the 10pf capacitors to ground at the summing junctions in figure 4. adding those capacitors does start to peak the output noise of the isl55210, but this stage will be followed by a passive filter rolling that noise of f. a detailed discussion of the input referred noise figure for this transformer coupled fda topology may be found at: http://www.edn.com/design/analog/4400484/accurately- predict-measured-noise-figur es-for-transformer-coupled- differential-amplifiers--part-1-of-2-- for the default configuration on this isla214p50-55210ev1z board using the components shown in figure 4, the estimated noise figure will be 7.2db from a 50 ? source. converting that to an input referred spot noise voltage including a 50 ? source noise gives a very low 1.02nv/ hz. this is only for the amplifier stage, and not including any noise in the original source signal. delivering this to the adc inputs through the full signal path gain figure 4. amplifier power supply decoupling and input signal up to the amplifier inputs
application note 1837 6 an1837.0 may 3, 2013 of 5.6v/v yields a 5.7nv/ hz differential spot noise. combining this with the various noise elements within the isla214p50 will give a slight degradation in the resulting snr in the fft. those calculations are described in this article: ?deliver the lowest distortion and noise in a low power, wideband, adc interface ? part 2 of 4? http://www.planetanalog.com/ document.asp?doc_id=528177 the second adtl1-12 common mode choke transformer provides a very broadband, lo w insertion loss, element that forces balance in this differential signal path. testing with and without this element showed a significant improvement in the fda output 2 nd harmonic distortion at hi gher frequencies. this is an optional element in the desi gn and can be bypassed with the optional shorts, but the best sfdr will be achieved with this element included as it is in the standard board build. elements contributing to the passband flatness and higher frequency cutoff each of the elements in the signal path have fine scale rolloffs that need to be considered to achieve the final 0.8db flatness through the 100khz to 100mhz intended digitizer range for this example design board. the adt4-6t input transformer was selected mainly for its low frequency performance. while specified as -1db flat from 150khz to 200mhz, typical devices measure to have a -1db flatness span when driven from a 50 ? source to a 200 ? load of 40khz to 180mhz. this far exceeds the mini-circuits specified flatness region on the low frequency side which is very typical for these wideband baluns. figure 5 shows a comparison to measured and modeled transformer response with a 50 ? source to 200 ? load. since there is limited data at low frequencies in the vendor data sheet, no comparison is made to that. the measured curve is showing about -0.5db at 100khz and -0.3db at 100mhz. the spice model (used in subsequent simulations) is only attempting to match the high and low f -3db frequencies and the midband gain including the measured 0.2db insertion loss. that modeling a pproach is described in this article: ?measuring and modeling wideband baluns for application to adc input stages? http://www.planetanalog.com/au thor.asp?section_id=434&doc _id=558824& for a higher frequency range design, the ma/com maba-0096-cf48a0 measures in the same configuration to have a -0.5db flatness span from 300khz to 220mhz typically which would make it a good choice for 1mhz to 200mhz analog input span. the adt1-12 common mode choke following this actually has 0db insertion loss in this configuration at low frequencies. this increases to -0.2db midband with a -1db point at >1ghz with these higher 200 ? source and load impedances used at this point in the signal chain. the amplifier will have its own frequency response from these source impedances and gain setti ngs. having good simulation models for each of the elements in the design allow easy comparisons of options. setting up an isim pe circuit for the input stage of figure 4 gives a simulation circuit of figure 6. figure 5. adt4-6t response curves 3.0 3.5 4.0 4.5 5.0 5.5 6.0 100k 1m 10m 100m 1g measured modeled frequency (hz) figure 6. simulation circuit for the input stage part of the isla214p50-55210ev1z board
application note 1837 7 an1837.0 may 3, 2013 this is set up with the source v1 at a ?2? amplitude to generate the response from the input to c1 to v out as shown in figure 7. the amplifier circuit is expecting a 50 ? source impedance for best flatness. the extrinsic one sh own in figure 6 will produce a 6db loss to the board input of fi gure 4 but simulating with a source set to ?2? will remove that matching loss from the v out plot. the simulated response show s exceptional flatness down to 100khz and about -1db rolloff at 100mhz. that rolloff will be equalized a bit with a slight peaking in the interstage filter design. interstage filter from the fda outputs to the adc the signal path from the isl55210 to the adc is ac coupled, allowing the amplifier and adc to operate at the common-mode voltage that optimize each device?s performance. as delivered, the differential output of the isl55210 operate with a common mode voltage that is left to default to the internal 1.2v value. this can be adjusted to differen t set point via an optional path. the interstage passive circuit provides an ac coupled, 3 rd order low pass filter. built into this filter are an adc common mode voltage servo loop which controls the common-mode dc voltage delivered to the adc input pins and a wideband passive sense path going differential to single ended to directly measure the response shape to the adc inputs. the circuit as delivered is shown in figure 8. figure 7. predicted response shape to v out for a 50 ? source to the input of c1 4 6 8 10 12 14 18 10k 1m 10m 100m 1g frequency (hz) 16 100k 20 (db) figure 8. output interface from isl55210 to the isla214p50 differential inputs
application note 1837 8 an1837.0 may 3, 2013 again, the green elements are optional and not populated. the non-populated elements connecting into c1005 would be the fda v cm adjustment if desired. as delivered, c1005 simply decouples the isl55210 v cm control pin which defaults internally to 1.2v on 3.3v supply. not shown is a jumper on j2 from pin 2 to 3 to connect in the servo loop adc v cm control path. the isla214p50 adc uses an unbuffered sample and hold and will therefore sink a sample rate dependent common-mode current which will give a sample rate dependent voltage drop from the midpoint of resistors r1015 -- > r1018 and r2011, r2012. the servo loop is used primarily to counteract the sample-rate dependent voltage drop to deliver a fixed common- mode voltage to the adc input pins across all sample clock rates. an alternate connection uses pin 2 to 1 on jumper j2 and populates r1019 to provide a fixed thevenin source for the adc v cm control. this provides a simpler solution when the design is known to be a fixed clock rate design. numerous options exist for providing this adc input v cm voltage for different designs. the two offered on this board, along with several others, are detailed in this article: ? advantages to precise input common mode voltage control to high performance high speed adc?s? http://www.edn.com/design/analog/4389814/advantages-to- precise-input-common-mode-voltage-control-to-high- performance-high-speed-adcs?page=0 the differential signal at the outputs of the isl55210 proceeds from left to right in figure 8 through the 40.2 ? resistors to a differential 5.6pf capacitor and then into the 1 f dc blocking capacitors. those level shift the dc operating voltage from the fda outputs to the required common mode voltage at the adc inputs. the rest of the passive filter from there is pair of series 82nh inductors then into a parallel rc network comprised of the 4 resistor network feeding the diff erential to single ended sense path at the output of t4, an external 1pf differential capacitor and then the internal rc elements of the adc. a final circuit element senses the average common mode voltage at the adc inputs using the 2-20k ? resistors and feeds that into a low frequency servo loop amplifier using the isl28113 which then feeds a dc control voltage to the center of the 4-resistor string that acts to control the adc co mmon mode operating voltage to the reference voltage applied at the isl28113 v+ input. critical to understanding the response shape are the estimated internal adc elements as shown in the simulation circuit for this interface in figure 9 (this element numbering here does not follow the build schematic of figure 8) at the far right the adc is mode led as 2-clock rate dependent current sources (1.3ma here for the 500msps case) with an internal lumped element 16pf in parallel with 200 ? . the probes show the dc operating voltages where the 2.22v at the isl28113 outputs gets back to the targeted 0.96v at the adc inputs as those icm currents pull down through the dc impedances from the output of the isl28113. the internal adc elements combine with the external rc elements to give the simulated frequency response sh ape from the isl55210 outputs to the adc inputs shown in figure 10. this slight peaking is intended to equalize some of the rolloff up to the fda outputs but then bandlimit quickly above 100mhz. the v test of figure 8 provides an easy means to verify the frequency response shape from th e board input to the adc. the 4 resistor network feeding t4 in figure 8 shows a about a 25 ? source to each leg of the 1:1 transformer while its total impedance across the signal path is part of the filter design. this path will have considerable insertion loss ( -31.8db) but an accurate replica of the response shape as shown for 2 boards measured in figure 11. figure 9. simulation circuit fo r the interstage filter and v cm servo loop figure 10. targeted response shape in the interstage filter to the adc -6.0 -5/5 -5.0 -4.5 -4.0 -3.0 20m 60m 80m 100m 150m frequency (hz) -3.5 40m -2.5 dbv (|2-pos - |1-pos)/db
application note 1837 9 an1837.0 may 3, 2013 the adc also can be used to measure the signal path frequency response by holding a constant input power while stepping the frequency and recording the change in the dbfs out of the fft. this is shown on a linear frequency scale in figure 12 targeting a single tone at -12dbfs out of the fft at 30mhz, then holding constant input power and measuring the drop in dbfs as the frequency is stepped up. clearly the overall response shape is doing a good job of providing approximately 15db gain from board edge with <-1db rolloff to 100mhz. it is important for distortion reasons to stay away from the rolloff regions of the input step up transformer. the intended minimum frequency in this application is 100khz, well above the 40khz -1db measured on t he adt4-6t while the maximum intended frequency is 100mhz which is also well below the measured 180mhz -1db frequency on the adt4-6t. the interstage filter bandlimits the broadband noise out of the isl55210 to reduce snr degradat ion through the adc while also providing a bit of hd2 and hd3 at tenuation from the fda outputs to the adc inputs. for instance, a single tone 80mhz at the fda output pins will have an hd2 at 160mhz and an hd3 at 240mhz. the response shape of figure 11 suggests that hd2 term will get about 4db attenuation while the hd3 term will get 13db attenuation to the adc inputs. clock and control options the board offers several optional features that are in some cases not fully populated. the clock options and two other control inputs are shown in figure 13. the populated path for the adc clock is the lower right input through the tc4-19g2 transformer. it is this path that must have a valid clock input (usually a filtered sine wave) when the konverter software is started. lab tests here were at 10dbm to 14dbm input levels at j4. an alternate clock path is through an adi ? adclk905 differential output ecl clock driver. that path is populated by adding the sma at the buffered clock input point at j5, adding the ecl clock buffer chip, populating the coupling caps (c46 and c47) and removing the coupling caps from the transformer input path (c28 and c29). this alternate clock path allows much lower power sine wave inputs into what is essentially a very low jitter differential output comparator. its inputs are also differential, but one side is biased to the midpoint threshold to run single ended input. a very low phase noise sine wave inputs as low as -2dbm will generate the necessary output clock transition times to drive the adc clock inputs. the clock chip includes internal 50 ? termination for the sine wave source. a similar signal path is shown in figure 13 just below the alternate clock path that provid es an adc sync operation if populated. to use this, add an sma connector at j7 and the clock chip at u9. refer to the adc data sheet for the operation of this control path. the amplifier may also be di sabled through a high speed interface by populating the pd sma input through u5, a cmos inverter. as delivered, the dc coupled 50 ? termination resistor holds the input at ground providing a 3.3v output to the disable control line on the isl55210. this holds the amplifier in the enabled mode while connecting the sma and driving that signal to a logic high, will disable the amplifier. it is important to recognize that even in the disabl e mode a signal path to the adc will be present through the feed back resistors. it will be significantly attenuated from the active mode, but it will not be an open circuit. the isl55210 includes two desirable features when disabled. 1. there are internal back to back diodes across the input summing junctions to limit the amplitude of high overdrive signals when disabled (or when acti ve as well). in disable, this limits the maximum differential voltage available across the inputs to a diode voltage which is then all that can feed forward to the adc ? at an attenuated level. 2. a low power monitor circuit holds the output v cm voltage at the same set point during disable as for the active mode. this prevents a long turn on time (or ac coupled common mode voltage spikes) through blocking caps in the output interface circuit as the amplifier cycles through enable /disable modes ? further protecting the adc from out of range inputs. contact the factory for assistance in exercising these clock and control options. figure 11. overall frequency response shape from the board input to the adc figure 12. zoomed in response shape using the adc to measure flatness -50 -45 -40 -35 -30 -25 -20 -15 -10 1m 1.0m 100m 1g m e a s u r e d s 2 1 ( d b c ) board #1 board #2 frequency (hz) -16 -15 -14 -13 -12 -11 -10 30 40 50 60 70 80 90 100 110 120 130 db fs frequency (mhz) board #1 board #2
application note 1837 10 an1837.0 may 3, 2013 figure 13. clock and control portion of the signal path schematic
application note 1837 11 an1837.0 may 3, 2013 combined fft performance for the input interface circuit and the adc the starting point for the dynamic range of the isla214p50-55210ev1z board would be the reported performance of the adc only in its typical 2-transformer input evaluation board circuit. the typical adc only evm is described here: http://www.intersil.com/conten t/dam/intersil/documents/isla/ isla214ir72ev1z_schem_layers.pdf while the isla214p50 data sheet is available here: http://www.intersil.com/content/dam/intersil/documents/fn75 /fn7571.pdf the snr shown in figure 2 from the adc data sheet (and repeated here) is actually snrfs. combining the information in these plots along with the specification table suggests the following typical numbers for the adc only up through 100mhz inputs: 1. snrfs 72.6db 2. sfdr 82dbc to 84dbc 3. hd2 < -84dbc 4. hd3 < -80dbc the snrfs will certainly drop from this 72.6db by some amount due to the added integrated noise presented to its inputs over a simple transformer input test. the hd2 and hd3 will show a complex result when combined with the adc where that testing will be done here at -2dbfs. recognizing that the midrange input frequencies will get little interstage filter help on the hd2 and hd3 terms, the 40mhz fft of fi gure 16 is showing that the intrinsic dynamic range up to the fda outputs is so good as to produce almost no degradation in adc only operation. for this 283mv p-p single tone input at 40.07mhz that is bandpass filtered and delivered to the sma input, the: 1. snrfs has dropped from 72.6dbc to 71.9dbc 2. sfdr is bit better than typical at 89dbc vs the adc only 82dbc to 84dbc 3. hd2 has improved to -89dbc from adc only of approximately -85dbc 4. hd3 has improved to -93dbc fr om a typical -88dbc looking at figure 15 at 40mhz testing two boards for swept input frequency snrfs gives the plot of figure 17 where the re sult has dropped about 1db from the adc only data. the swept frequency hd2 performance actually improves slightly over the adc only plots. this might be attributed to the -2dbfs target but certainly shows no degradation using the very high dynamic range input interface circuit implemented on this board. the swept frequency hd3 also seems slightly improved over the typical adc only plots. these plots are showing some degradation in snrfs, and a slight improvement on the hd 2 and hd3 performance. here, however, the -2dbfs input level is only 283mv p-p at board edge vs a much higher level for the typical adc characterization circuit. the harmonic distortion performance is the combined result of many elements in the design. hence, it is very difficult to make too strong a claim on the worst case distortion. the limited testing here seems to indicate a <-80dbc performance is certainly being delivered where even <-85dbc seems possible. while the signal path circuit here may seem a bit involved, it is converting from single ended input and delivering a bandlimited response to the adc with precise common mode control and exceptionally low noise and di stortion using <120mw total. since the fft?s are showing nearly as good performance as the adc itself, this solution is equivalent to a 14-bit, 500msps adc requiring only 300mv p-p single ended input for -1dbfs. figure 14. snrfs and sfdr vs f in using 500msps clock and targeting -1dbfs and then the swept frequency on just those hd2 and hd3 terms from figure 3 in the isla214p50 data sheet. figure 15. hd2 and hd3 vs f in using 500msps clock and targeting -1dbfs 55 60 65 70 75 80 85 90 95 0 100 200 300 400 500 600 sfdr snr sfdr (excluding h2, h3) input frequency (mhz) snr (dbfs) and sfdr (dbc) -95 -90 -85 -80 -75 -70 -65 -60 -55 0 100 200 300 400 500 600 hd2 hd3 input frequency (mhz) hd2 and hd3 magnitude (dbc)
application note 1837 12 an1837.0 may 3, 2013 figure 17. 500msps snrfs results for 2 isla214p50-55210ev1z boards figure 18. 500msps hd2 results for 2 isla214p50-55210ev1z boards figure 19. 500msps hd3 results for 2 isla214p50-55210ev1z boards figure 16. 40mhz input, 500msps fft from the konverter software 71.0 71.5 72.0 72.5 0 204060 80100 snrfs (db) input frequency (mhz) board #1 board #2 730 -110 -105 -100 -95 -90 -85 0 2040 6080100 board #1 board #2 hd2 (dbc) input frequency (mhz) -105 -100 -95 -90 -85 -80 0 20406080100 board #1 board #2 hd3 (dbc) input frequency (mhz)
application note 1837 13 an1837.0 may 3, 2013 tested performance over adc input v cm setting using the available adc common mode voltage servo loop feature, it is an easy matter to move the dc operating voltage at the adc inputs around and verify the range of good performance. using the same basic targets of -2dbfs with a fixed fin at 30mhz, one test board was swept from 0.9v cm to 1.1v cm . the figure of merit here was the thd as the various spurious are moving around a lot with v cm but the overall thd is relatively constant. figure 20 shows this test at two clock frequencies. the 500msps data is relatively insensitive to v cm input over this range showing very robust performance to varying v cm input voltages. overall improved spurious performance has been observed with this adc at lower clock rates and the 450msps data shows a bit more sensitivity to the adc input v cm setting. in this test, the dc operating points through the fda are not changing, none of the response shapes are changing up to the adc, the only variable is the dc average input voltage for the signal being delivered to the adc input pins. this is exercising fine scale input impedance nonlinearities in the adc against the source impedance of the filter. while very robust over a relatively wide input v cm range, the plot above suggested a 0.96v cm set point for this board and that is the delivered condition. changing the filter design and/or adc migh t suggest a reset on that target adc v cm voltage. this is easily accomplished using the v cm servo loop feature. tested performance with fixed f in and narrow clock range around 500msps since it seemed the fft improved somewhat in dropping just below 500msps, a 50msps range around 500msps was evaluated with a fixed 50mhz inpu t generating a -2dbfs in the fft. looking again at the thd si nce the various spurious are moving around a lot with ea ch test, gives the example performance of figure 21. this is indeed showing a pre tty rapid improvement in thd dropping below 500msps and a good guardband above 500msps for acceptable performance. while it is not suggested that the adc be operated above 500msps, this plot does show a good margin above that before catastrophic fall off in the thd. this is intended to add over temperature margin in the adc performance. 2-tone, 3 rd order im3 testing since the board passes frequenc ies to 100mhz, duplicating the 70mhz im3 performance reported in the isla214p50 data sheet will show the combined performance for the adc and the interface circuit. the plot from the isla214p50 data sheet (figure 16 there) is shown in figure 22. this is reporting a -88dbfs 3 rd order intermodulation spurious for the 2 close in spurs at 3 f in around the midpoint ? that would be at 69mhz and 71mhz here. converting this dbfs to dbc gives -80dbc for the im3. for this broadband test, the im2 is also apparent at 141mhz and 1mhz. duplicating this set up with slightly lower carriers (-8dbfs vs -7dbfs on the adc data sheet) at 69.5mhz and 70.5mz gives the wideband fft of figure 23. in this case, with 2 test tone inputs, the reported snr does not compute correctly. it is easy to see here that the im2 at 140mhz has been suppressed quite a lot by the combined excellent even order suppression in the interface circuit and the interstage filter. the other im2 at 1mhz is also lower. zooming in on a 65mhz to 75mhz range in figure 24 shows exceptionally low 3 rd order terms in this solution. figure 20. thd vs adc input common mode voltage thd (-dbc) -89 -88 -87 -86 -85 -84 -83 0.90 0.95 1.00 1.05 1.10 1.15 1.20 v cm setting at adc inputs (v) 500msps 450msps figure 21. thd vs f clk around the 500msps specified maximum clock rate figure 22. isla214p50 im3 plot at 70mhz and 71mhz inputs frequencies -88 -86 -84 -82 -80 -78 450 470 490 510 530 550 t h d ( db c ) f clk (mhz) thd 0 50 100 150 200 250 -120 -100 -80 -60 -40 -20 0 frequency (mhz) amplitude (dbfs) imd2 imd3 2nd harmonics 3rd harmonics imd3 = -88dbfs
application note 1837 14 an1837.0 may 3, 2013 figure 23. full nyquist span fft for a 70mhz im3 test figure 24. zoomed in fft arou nd the carrier frequencies
application note 1837 15 an1837.0 may 3, 2013 the data markers are showing -11dbfs on the carriers and -105dbfs on the 3 rd order intermodulation spurious terms. this is the raw data where the actual carriers were each -8dbfs and are reduced 3db in the data by the 4-term blackman harris windowing being used. in any case this is showing -94dbc im3 performance at 70mhz. the bandpass filter shape can also be seen easily in the noise floor. this -94dbc far exceeds the adc performance shown in figure 22 which might be attributed to a lower spurious input test signal using the 15db gain in front of the adc here or perhaps poorer im3 in the interface elements on the adc only evm board. the isl55210 is very nearly un- measurable for oip3 at 70mhz and that is clearly reflected in the significantly improved performanc e of figure 24. dropping the test power levels showed an intercept performance in the fft where dropping only 3dbm on th e two test powers dropped the spurious 9db into the noise floor. appendix a: low phase noise rf generators some examples of low phase noise generators suitable for high resolution adc clock and source signal generation in test include: 1. rohde & schwarz: sma100a 2. agilent 8664a 3. gigatronics 6080a for fixed 500msps clock operation, the crystek rfpro33-500.00 offers a simple solution. this device operates within an sma body and requires a 3.3v supply to produce the required clock to operate this evm. bandpass filtering on the clock always helps the snr performance for any of these sources. most of the data here was taken with the 8664a which seemed to give the best snrfs results. tested performance over a wide range of clock frequency and fin as the clock rate is reduced several slight changes in the response can be expected. 1. the icm current into the 2 adc inputs will decrease. using the servo loop amplifier will act to hold the adc input v cm voltage constant as the clock rate is changed. 2. the adc input resistance will increase slightly. the 200 ? internal value shown in the simulation circuit of figure 9 is a combination of an extrinsic 300 ? element and the effective resistance of a sampling cap. that impedance is approximately 1/(fs*3.3pf). as th e clock rate decreases, this impedance will increase moving the apparent input resistance up. by 200msps the total adc internal resistance is 250 ? . this shift will slightly change the response shape of the interstage filter. 3. reducing the clock rate gives every operation internal to the adc a bit more time to settle and improved dynamic range over the analog input frequency is observed. the following figures summarize the swept input frequency dynamic range vs fsample repeating the 500msps data for comparison to 450msps. these are all targeting a -2dbfs using very low phase noise sources and bandpass filtering on both the clock and fin. in general, at clock rates 450msps the hd2 and hd3 terms hold below -85dbc.
application note 1837 16 an1837.0 may 3, 2013 500msps 450msps figure 25. 500msps snrfs figure 26. 450msps snrfs figure 27. 500msps hd2 figure 28. 450msps hd2 figure 29. 500msps hd 3 figure 30. 450msps hd3 71.0 71.5 72.0 72.5 0 204060 80100 snrfs (db) input frequency (mhz) board #1 board #2 730 71.0 71.5 72.0 72.5 73.0 0 20 40 60 80 100 snrfs (db) input frequency (mhz) board #1 board #2 -110 -105 -100 -95 -90 -85 020406080100 board #1 board #2 hd2 (dbc) input frequency (mhz) -110 -105 -100 -95 -90 -85 0 20406080100 hd2 (dbc) input frequency (mhz) board #1 board #2 -105 -100 -95 -90 -85 -80 0 20406080100 board #1 board #2 hd3 (dbc) input frequency (mhz) -105 -100 -95 -90 -85 -80 0 20406080100 hd3 (dbc) input frequency (mhz) board #1 board #2
application note 1837 17 an1837.0 may 3, 2013 400msps 350msps figure 31. 400msps snrfs figure 32. 350msps snrfs figure 33. 400msps hd 2 figure 34. 350msps hd2 figure 35. 400msps hd 3 figure 36. 350msps hd3 71.0 71.2 71.4 71.6 71.8 72.0 72.2 72.4 72.6 72.8 73.0 0 2040 6080100 input frequency (mhz) board #1 board #2 snrfs (db) 71.0 71.2 71.4 71.6 71.8 72.0 72.2 72.4 72.6 72.8 73.0 0 2040 6080100 input frequency (mhz) board #1 board #2 snrfs (db) -110 -105 -100 -95 -90 -85 0 20 40 60 80 100 hd2 (dbc) input frequency (mhz) board #1 board #2 -110 -105 -100 -95 -90 -85 0 20406080100 input frequency (mhz) board #1 board #2 hd2 (dbc) -105 -100 -95 -90 -85 -80 0 20406080100 hd3 (dbc) input frequency (mhz) board #1 board #2 -105 -100 -95 -90 -85 -80 0 20406080100 input frequency (mhz) board #1 board #2 hd3 (dbc)
application note 1837 18 an1837.0 may 3, 2013 300msps 250msps figure 37. 300msps snrfs figure 38. 250msps snrfs figure 39. 300msps hd 2 figure 40. 250msps hd2 figure 41. 300msps hd3 figure 42. 250msps hd3 71.0 71.2 71.4 71.6 71.8 72.0 72.2 72.4 72.6 72.8 73.0 0 2040 6080100 input frequency (mhz) board #1 board #2 snrfs (db) 71.0 71.5 72.0 72.5 73.0 0 2040 6080100 input frequency (mhz) board #1 board #2 snrfs (db) -110 -105 -100 -95 -85 0 20406080100 input frequency (mhz) board #1 board #2 hd2 (dbc) 90 -105 -100 -95 -90 -85 0 20406080100 hd2 (dbc) input frequency (mhz) board #1 board #2 -110 -105 -100 -95 -90 -85 -80 0 20406080100 h d 3 ( d b c ) input frequency (mhz) board #1 board #2 -105 -100 -95 -90 -85 -80 0 20406080100 hd3 (dbc) input frequency (mhz) board #1 board #2
application note 1837 19 an1837.0 may 3, 2013 board options while this board shows a complete example of a low power, high dynamic range, single to differen tial amplifier stage, numerous options can be implemented on this board. principally, the gain in the amplifier can be easily changed modifying the feedback resistors up or down (r1008, r1 011). the output filter can be re-designed for a different passband. l1004 is included (figure 8) to implement bandpass fi lters on this board as well. the isla214p50 is part of a large pin compatible adc family. those can be dropped into this board replacing the isl214p50 but will require some redesign in the filter for different adc input impedances and a reprogramming through the konverter software for the specific adc. contact the factory for assistance with this. table 2 summarizes the pin compatible, high performance, adc family supported by this single daughtercard. these span a large range in bits and maximum clock rate where lower clock rates run lower power in each family of devices. 200msps figure 43. 200msps hd2 f igure 44. 200msps hd2 figure 45. 200msps hd3 71.0 71.5 72.0 72.5 73.0 0 2040 6080100 input frequency (mhz) board #1 board #2 snrfs (db) -110 -105 -100 -95 -90 -85 0 20406080100 hd2 (dbc) input frequency (mhz) board #1 board #2 -105 -100 -95 -90 -85 0 20406080100 hd3 (dbc) input frequency (mhz) board #1 board #2 table 2. pin compatible high performance adc family part number resolution (bits) maximum sample rate (msps) power consumption (mw) isla216p25 16 250 785 isla216p20 16 200 720 isla216p13 16 130 615 isla214p50 14 500 835/900 (note) isla214p25 14 250 450 isla214p20 14 200 410 ISLA214P13 14 130 360 isla214p12 14 125 310 isla212p50 12 500 823/892 (note) isla212p25 12 250 440 isla212p20 12 200 405 isla212p13 12 130 355 note: i2e disabled/enabled.
application note 1837 20 an1837.0 may 3, 2013 full signal path schematic the full schematic from input to adc pins is shown in figure 46. figure 46. full signal path schematic
application note 1837 21 an1837.0 may 3, 2013 the following bom is for the entire isla214p50-55210ev1z board. it includes some elements not described here that are associate d with the adc operation common to its evm bo ard ? the isla214p50ir72ev1z. the main focus of this board is to add a very high linearity input interface circuit that has been thoroughly described here. elements in the following bom that do not have a des cription in the comments column are not part of the signal path but common to the adc only evm board. isla214p50-55210ev1z bill of materials shaded rows unpopulated part number qt y units reference designator comment description mfr. mfr. part isla214p50- 55210ezrvbpcb 1 ea blank board pwb-pcb, isla214p50- 55210ez, revb, rohs imagineering inc isla214p50- 55210ezrvbpcb 160x14w473mv4t-t 2 ea c1004, c1009 isl55210 supply decoupling cap-x2y, smd, 0603, 0.047f, 16v, 20%, x7r, rohs johanson dielectrics inc 160x14w473mv4t grm188r71e105ka12d-t 4 ea c1007, c1010, c1012, c1019 signal path blocking caps cap, smd, 0603, 1f, 25v, 10%, x7r, rohs murata grm188r71e105ka12d h1044-00100-50vr25-t 2 ea cterm1, cterm2 response shaping at inverting summing junctions cap, smd, 0402, 10pf, 50v, 0.25pf, np0, rohs avx 04025u100cat2a h1044-00101-50v5-t 1 ea c1022 isl28113 supply decoupling cap cap, smd, 0402, 100pf, 50v, 5%, c0g, rohs murata grm1555c1h101jz01d h1044-00102-16v10-t 4 ea c28, c29, c48, c58 adclk905 supply decoupling & adc transformer clock path cap, smd, 0402, 1000pf, 16v, 10%, x7r, rohs tdk c1005x7r1c102k h1044-00103-16v10-t 3 ea c30, c1020, c1021 vcm servo loop caps around isl28113 & clock transformer centertap ac gnd cap, smd, 0402, 0.01f, 16v, 10%, x7r, rohs tdk c1005x7r1c103k h1044-00104-16v10-t 17 ea a) c4, c5, c20, c22, c24, c27, c33, c34, c42 various supply decoupling caps, largely on the bottom of the board. cap, smd, 0402, 0.1f, 16v, 10%, x7r, rohs venkel c0402x7r160-104kne h1044-00104-16v10-t 0 ea b) c43, c44, c45, c50, c56, c113, c114, c115 various supply decoupling caps, largely on the bottom of the board. cap, smd, 0402, 0.1f, 16v, 10%, x7r, rohs venkel c0402x7r160-104kne h1044-00105-10v10-t 1 ea c1014 vcm feedback point decoupling cap. cap, smd, 0402, 1.0f, 10v, 10%, x5r, rohs murata grm155r61a105ke15d h1044-005r6-50vr5-t 1 ea c16 3rd order interstage differential filter cap cap, smd, 0402, 5.6pf, 50v, 0.5pf, np0, rohs murata grm1555c1h5r6dz01d h1044-dnp 0 ea a) c8, c9, c10, c11, c12, c13, c14, c15 cap, smd, 0402, dnp-place holder, rohs h1044-dnp 0 ea b) c25, c35- c38, c46, c47 optional clock and control signal path caps not populated cap, smd, 0402, dnp-place holder, rohs h1045-00010-50vr1-t 1 ea cdiff 3rd order interstage differential filter cap cap, smd, 0603, 1.0pf, 50v, 0.1pf, np0, rohs tdk c1608c0g1h010b h1045-00102-50v10-t 1 ea c32 clk input to transformer cap, smd, 0603, 1000pf, 50v, 10%, x7r, rohs avx 06035c102kat2a h1045-00103-16v10-t 2 ea c52, c54 adclk905 input signal coupling cap, smd, 0603, 0.01f, 16v, 10%, x7r, rohs venkel c0603x7r160-103kne
application note 1837 22 an1837.0 may 3, 2013 h1045-00104-25v10-t 6 ea c2, c3, c53, c55, c1005, c1023 various supply and bias line decoupling caps. cap, smd, 0603, .1f, 25v, 10%, x7r, rohs murata grm39x7r104k025ad h1045-00105-50v10-t 4 ea c49, c51, c57, c59 supply decoupling on the adclk905's cap, smd, 0603, 1f, 50v, 10%, x5r, rohs tdk c1608x5r1h105k h1045-dnp 0 ea c1003, c1008, c1017, c1018 alternate isl55210 supply decoupling & vtest path coupling cap, smd, 0603, dnp-place holder, rohs h1065-00105-16v10-t 1 ea c1002 main 3.3v supply line decoupling cap, smd, 1206, 1f, 16v, 10%, x7r, rohs panasonic ecj-3fb1c105k h1112-00336-16v10-c-t 4 ea c1, c6, c7, c31 supply decoupling cap-tant, smd, c, 33f, 16v, 10%, rohs avx tajc336k016rnj h1121-00475-10v10-b-t 1 ea c1001 3.3v supply decoupling to isl55210 cap-tant, low esr, smd, b, 4.7f, 10v, 10%, 3.5 ? , rohs kemet t491b475k010at 0603cs-82nxglu 2 ea l1002, l1003 signal path 3rd order filter inductors coil-rf inductor, smd, 0603, 82nh, 2%, 400ma, rohs coilcraft 0603cs-82nxglu 142-0701-851 1 ea input analog input signal end launch sma conn-rf, sma jack, 50 ? , bmt, tab-end launch, rohs johnson components 142-0701-851 22-28-4360-1x3 1 ea j2 jumper to select adc vcm set path, defaulted to use the servo loop with pins 2 & 3 shorted. conn-header, 1x3, brkawy-1x36, 2.54mm, 0.240x0.125, rohs molex 22-28-4360 5002 1 ea tp1 sense point for average cm at adc input pins conn-mini test point, vertical, white, rohs keystone 5002 5004 1 ea amplifier +3.3v sense point for the 3.3v supply to the signal path amplifier conn-mini test point, vertical, yel, rohs keystone 5004 5011 1 ea gnd gnd connector tap into for setting vcm voltage with dvm conn-multi-purpose test pt, blk, rohs keystone 5011 55091-1875 1 ea j6 mezzanine connector on board bottom to mate to motherboard conn-header, smd, dual row, 180p, 0.635pitch, 6mmstack, rohs molex 55091-1875 70280-0458-2x2 2 ea jp1, jp2 headers to select adc options. only jp1 is used with jumper connected set of pins closer to input conn-header, 2x2, brkawy-2x50, 2.54mm, rohs molex 70280-0458 87832-1420 1 ea j1 cpld connector conn-header, shrouded, smd, 14p, 2mmpitch, center slot, rohs molex 87832-1420 isla214p50-55210ev1z bill of materials shaded rows unpopulated (continued) part number qt y units reference designator comment description mfr. mfr. part
application note 1837 23 an1837.0 may 3, 2013 901-144-8rfx 1 ea j4 default clock input sma to xfmr path conn-rf, sma jack, 50 ? , pcb mnt, straight, rohs amphenol 901-144-8rfx spc02syan 2 ea jp1-pins 3-4, j2-pins 2-3. connecting jumpers on the jp1 and j2 posts conn-jumper, shorting, 2pin, black, gold, rohs sullins spc02syan hz1206e601r-10-t 2 ea l1001, l1005 +3.3v supply line ferrites to isl55210 and isl28113 ferrite-emi chip, smd, 1206, 600 ? , 500ma, rohs laird technologies hz1206e601r-10 mmz2012r102a-t 14 ea l3, l4, l8, l10-l20 ferrite bead, smd, 0805, 1k, 0.5a, 100mhz, rohs tdk mmz2012r102a 24fc128-i/sn 2 ea u2 u3 back side components ic-i2c serial eeprom, 8p, soic, 128 kbit, rohs microchip technology 24fc128-i/sn isl28113fhz 1 ea u10 adc vcm control servo loop op amp ic-rrio op amp, 5p, sot-23- 5, rohs intersil isl28113fhz isl55210irtz 1 ea u7 signal path fully differential amplifier ic-differential amp, 16p, tqfn, 3x3, rohs intersil isl55210irtz isla214p50irz 1 ea u1 adc ic-14-bit, 500msps a/d converter, 72p, qfn, 10x10, rohs intersil isla214p50irz sn74ahc1g04dbvr-t 1 ea u5 isl55210 disable control line inverter ic-single inverter gate, 2v-5.5v, 5p, sot-23-5, rohs texas instruments sn74ahc1g04dbvr xc2c64a-7vqg44c 1 ea u4 ic-cr-ii cpld, smd, 44p, vqfp, 64macrocells, 10x10, rohs xilinx xc2c64a-7vqg44c 3299w-1-502lf 1 ea r1043 adc vcm adjust pot pot-trim, th, 5k, 0.5w, 10%, 3p, 3/8, rohs bourns 3299w-1-502lf h2510-00200-1/16w1-t 1 ea r1031 isolating resistor into isl28113 summing junction res, smd, 0402, 20 ? , 1/16w, 1%, tf, rohs panasonic erj2rkf20r0 h2510-003r9-1/16w1-t 2 ea r2011, r2012 kickback isolation at adc input pins res, smd, 0402, 3.9 ? , 1/16w, 1%, tf, rohs vishay/dale crcw04023r90fked h2510-00r00-1/16w-t 7 ea r53, r54, r1009, r1010, r1118, r1020, r1035 various shorting paths in signal path circuit res, smd, 0402, 0 ? , 1/16w, 5%, tf, rohs venkel cr0402-16w-00t h2510-01000-1/16w1-t 4 ea r55, r56, r1006, r1007 input termination & gain elements, and adclk905 output load res, smd, 0402, 100 ? , 1/16w, 1%, tf, rohs venkel cr0402-16w-1000ft h2510-01001-1/16w1-t 21 ea a) r1, r4-r13, r30, r36, r38, r42, r52, r57, res, smd, 0402, 1k, 1/16w, 1%, tf, rohs venkel cr0402-16w-102jt h2510-01001-1/16w1-t 0 ea b) r58, r59, r60, r1041. res, smd, 0402, 1k, 1/16w, 1%, tf, rohs venkel cr0402-16w-102jt isla214p50-55210ev1z bill of materials shaded rows unpopulated (continued) part number qt y units reference designator comment description mfr. mfr. part
application note 1837 24 an1837.0 may 3, 2013 h2510-01002-1/16w1-t 2 ea r46, r1034 res, smd, 0402, 10k, 1/16w, 1%, tf, rohs panasonic erj-2rkf1002x h2510-02000-1/16w1-t 2 ea r27, r1022 r1022 part of vcm servo loop. res, smd, 0402, 200 ? , 1/16w, 1%, tf, rohs panasonic erj-2rkf2000x h2510-02002-1/16w1-t 3 ea r1032, r1033, r1042 r1032, r1033 part of vcm servo loop res, smd, 0402, 20k, 1/16w, 1%, tf, rohs panasonic erj2rkf2001 h2510-02320-1/16w1-t 1 ea r1021 adc vcm output pulldown res, smd, 0402, 232 ? , 1/16w, 1%, tf, rohs venkel cr0402-16w-2320ft h2510-040r2-1/16w1-t 2 ea r1013, r1014 differential 3rd order filter first resistors res, smd, 0402, 40.2 ? , 1/16w, 1%, tf, rohs panasonic erj-2rkf40r2x h2510-054r9-1/16w1-t 2 ea r48, r49 sync output series elements res, smd, 0402, 54.9 ? , 1/16w, 1%, tf, rohs vishay/dale crcw040254r9fked h2510-07151-1/16w1-t 1 ea r1044 res, smd, 0402, 7.15k, 1/16w, 1%, tf, rohs panasonic erj-2rkf7151x h2510-095r3-1/10w1-t 2 ea r50, r51 sync output shunt elements res, smd, 0402, 95.3 ? , 1/16w, 1%, tf, rohs panasonic erj-2rkf95r3x h2510-dnp 0 ea a) r3, r35, r16, r14 r15, r40, r41, r1019 res, smd, 0402, dnp, dnp, dnp, tf, rohs h2510-dnp 0 ea b) rbypass1- rbypass4, rterm1, optional bypass elements around input transformers res, smd, 0402, dnp, dnp, dnp, tf, rohs h2511-00r00-1/10w-t 3 ea r32, r33, r1000 res, smd, 0603, 0 ? , 1/10w, tf, rohs venkel cr0603-10w-000t h2511-01001-1/10w1-t 2 ea r62, r63 res, smd, 0603, 1k, 1/10w, 1%, tf, rohs panasonic erj-3ekf1001v h2511-01002-1/10w1-t 1 ea r34 res, smd, 0603, 10k, 1/10w, 1%, tf, rohs koa rk73h1jt1002f h2511-026r7-1/10w1-t 2 ea r1016, r1017 sense path divider output to 1:1 transformer res, smd, 0603, 26.7 ? , 1/10w, 1%, tf, rohs panasonic erj-3ekf26r7v h2511-04701-1/10w1-t 6 ea r2, r29, r31, r37, r39, r61 res, smd, 0603, 4.7k, 1/10w, 1%, tf, rohs yageo 9c06031a4701fkhft h2511-049r9-1/10w1-t 1 ea rterm3 disable input (isl55210) termination to ground at logic gate res, smd, 0603, 49.9 ? , 1/10w, 1%, tf, rohs venkel cr0603-10w-49r9ft h2511-05490-1/10w1-t 2 ea r1015, r1018 sense path divider output to 1:1 transformer res, smd, 0603, 549 ? , 1/10w, 1%, tf, rohs venkel cr0603-10w-5490ft h2511-dnp 0 ea r1001, r1002, r1004, r1005, rterm2 alternate vcm setup for fixed clock and divider to disable logic input res, smd, 0603, dnp-place holder, rohs rr0510p-4990-d-t 2 ea r1008, r1011 res, smd, 0402, 499 ? , 1/16w, 0.5%, thinfilm, rohs susumu co., ltd rr0510p-4990-d isla214p50-55210ev1z bill of materials shaded rows unpopulated (continued) part number qt y units reference designator comment description mfr. mfr. part
application note 1837 25 intersil corporation reserves the right to make changes in circuit design, software and/or specifications at any time without n otice. accordingly, the reader is cautioned to verify that the application note or technical brief is current before proceeding. for information regarding intersil corporation and its products, see www.intersil.com an1837.0 may 3, 2013 b3fs-1000p-t 1 ea sw1 adc reset button switch-push, th, 6mm, off- mom, spst-no, 100gf, rohs omron b3fs-1000p adt1-1wt+ 1 ea t4 vtest path output transformer transformer-rf, smd, 6p, case cd542, 0.5w, 30ma, rohs mini-circuits adt1-1wt+ adt4-6t+ 1 ea t1 *(pin 1 at upper left corner) input step up transformer transformer, smd, 6p, 7.8x5.5, 50 ? , 0.06-300mhz, rohs mini-circuits adt4-6t+ adtl1-12+ 1 ea t2 *(pin 1 at upper left corner) input common mode choke transformer transform-rf, smd, 6p, casecd542, 20-1200mhz, 2w, rohs mini-circuits adtl1-12+ tc4-19g2+-t 1 ea t3 transformer for clock input transformer-rf, smd, 6p, at224-3, 50 ? , 1/4w, 30ma, rohs mini-circuits tc4-19g2+ 5x8-static-bag 1 ea place assy in bag. bag, static, 5x8, ziploc, rohs intersil 212403-013 dnp 0 ea j5, j7 sma do not populate or purchase dnp 0 ea l1004 optional filter for bp design to adc do not populate or purchase dnp 0 ea pd vtest sma do not populate or purchase dnp 0 ea r1003 2k ? 10 turn pot for the isl55210 vcm control path. do not populate or purchase dnp 0 ea r22-r26, r28 do not populate or purchase dnp 0 ea u6, u8, u9 adclk905 for u8, u9 do not populate or purchase label-serial number 1 ea affix label to bottom of pcb label-for serial number and bom rev # intersil label-serial number isla214p50-55210ev1z bill of materials shaded rows unpopulated (continued) part number qt y units reference designator comment description mfr. mfr. part

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